1. Field of the Invention
The present invention relates to driving techniques for supplying power to a load, and more particularly, to driving circuitry in full bridge or half bridge inverter applications having non-overlapping pulses for vertical branches of the bridge, i.e., low voltage channel and high voltage channel.
2. Description of the Related Art
FIG. 1a illustrates a typical structure of level shift stage circuit 10 in the prior art. The level shift stage circuit 10 is provided with two HV DMOS transistors 14 and 16 for providing SET and RESET pulses to a RS flip flop 12. The input pulses applied to the Driving logic block 18 are decomposed into SET and RESET short pulses synchronous to the rising edge and falling edge of input signal. The level shifter, i.e., the transistors 14 and 16 generates two pulses, SETBAR and RESETBAR. These pulses are inverted once and are then applied to the RS flip flop 12. The output Q of the RS flip flop 12 will generate one square wave pulse, which is applied to the external power MOS transistor 13 and via a driver 15. Referring FIG. 1b, it depicts the timing diagram of the input signal, the SET signal, and the RESET signal.
The most important feature in the translation function when driving pulses from low voltage side to high voltage side is that using high voltage MOS/DMOS or BJT (Bipolar Junction Transistor) transistors result in dissipation of power, increase of cost, and occupation of space.
Accordingly, there exists a need for a converter circuit which is able to minimize the number of the transistors and the dissipation of power.